[UPDATE]AMD Carrizo APU ISSCC 2022 Presentation Leaked - 5% IPC Gain With x86 Excavator, Die Consists of 3.1 Billion Transistors

Update: Since it's only about time that when AMD presents Carrizo APU at ISSCC 2022, we wanted to give some additional details on the Carrizo APU which tin can be plant below in the commodity. In case you are unable to find the mentioned details, y'all can browse at the very end of the article to find first benchmarks of AMD Carrizo APUs in 3DMark along with more detailed information on the dice size of the new bit.

AMD's Carrizo APU presentation to be displayed during the upcoming ISSCC 2022 effect has been leaked ahead of its time past Videocardz. The slides show all of what we have expected from Carrizo to be a mobility cadre that features the latest x86 Excavator cadre architecture and GCN graphics architecture, combining them to evangelize a full SOC design for mobility platforms.

Image Credits: Videocardz

AMD Carrizo APU Detailed - IPC Gains, Power Efficiency, Depression-Power States Explained

To start off this commodity, there's a few things nosotros need to recap first. AMD's Carrizo APU was displayed first by John Byrne (Former SVP and GM of AMD Computing & Graphics Business Unit of measurement) in tardily 2022. Since the launch, AMD has undergone several structural changes including John leaving the company while Lisa Su talking chair equally the CEO of the company. The first shock came when it was reported that Carrizo and Carrizo-L won't be a feature product for the desktop platform and will exist limited to mobility platforms only. The company volition now instead focus on a refresh based on current Kaveri APUs codenamed "Godavari" to satisfy consumers until they launch their Excavator powered "Bristol Ridge" APUs in 2022. It might also suggest that Carrizo's successor will be updated from the architecture side while desktop platforms will stay one step back with the current high-performance x86 node (Excavator).

Coming to the architecture of the APU itself, it was expected that similar Kaveri earlier it, Carrizo won't be a revolutionary fleck. Information technology is based on the electric current iteration of GCN architecture and the Excavator core itself is a more enhanced and derived class of the construction cores which started with Bulldozer in 2022. So we are looking at a nominal five% IPC gains from the new Excavator cores which shows AMD is following Intel footsteps in this field with the blue squad also offering a like IPC improvement on their latest 14nm Broadwell Uarch. The dice is still based on a 28nm node yet AMD has managed to optimize the overall chip blueprint by adding 29% more than transistors than Kaveri thanks to the high-density pattern library. This results in a iii.1 Billion transistor die that delivers 40% bottom power consumption and 23% bottom die area than its predecessor. The H.265 encode support allows 3.5 times transcode operation of Kaveri while the compute architecture enables the 8 GCN compute units (512 stream processors) a reduction of xx% in power consumption. AMD talks of a double digit increment in both the functioning and bombardment sector even so they are no where most the gains we expected earlier from Carrizo.

In terms of size, the Carrizo die measures at 244.62mm² on the 28nm node while Kaveri measures at 245mm² on the same procedure. The departure between both chips is that Carrizo ups the transistor count to 3.1 billion from Kaveri'south 2.41 billion count. The sudden reduction in the size of the die fifty-fifty when adding more ameliorate x86 performance was due to the fact that Excavator cores are smaller than Steamroller cores, measuring at but fourteen.48mm2 with a core transistor count of 102 million transistors. The L1 cache has likewise doubled on Carrizo to 32 KB per cadre from xvi KB. The overall core structure has 690 one thousand thousand transistors crammed in 1 partitioning while the rest of the transistors are dedicated to GCN cores that utilize HSA and compute engine advantage in full general purpose computing environments.

AMD Carrizo APU Power Optimization Features

We will get back to the technical bits in a moment after detailing the power optimization features. Based on the Excavator architecture, the Carrizo APUs are more denser with each cell being 35% smaller than Kaveri e.g. FPS/FMAC/I-Enshroud. AMD has also managed to create a more full general purpose GPU-Oriented stack that helps reach this new FIN stacking implementation compared to prior generation designs. On the graphics front, AMD achieves 18% leakage reduction and gate-timing with faster RVT devices that enables 10% higher frequency while consuming sipping the same level of power.

Then an 8 CU GCN module that previously shipped around 28W will be downwards to just 22W with Carrizo. AMD has implemented several AVFS modules inside the Excavator core that excerpt the truthful silicon speed capability of the core past balancing between the voltage, temperatures and bachelor headroom. This provides an additional ability reduction level over the High-density library gains. Lastly, AMD has introduced a new low power state on Carrizo called S0i3 which is also known as the Standby state that leaves only the ACP and FCH running and keeps everything else off to permit the chip to operate at just 50mW, conserving bombardment life. In idle state, the CPU, GPU and most of the PLL blocks would exist disabled to result in a 1.5W ability consumption. Voltage adaptive operations further lead to a 19% (CPU) and 10% (GPU) ability savings.

AMD Carrizo APU Features - What's Under The Hood?

We have already detailed previously almost the features that Carrizo will pack underneath its die. Some features presented in the slides mention a single, scalable infrastructure that volition be shared with Carrizo-L since we have known that both fries are pin-to-pin uniform. They come with GCN graphics supporting Mantle, DirectX 12 and Dual graphics. Both the single-chip integration of the APU and the southbridge are located on a single die and HSA ane.0 is fully implemented that also helps improve free energy efficiency. AMD will also add AVX2, BMI2, MOVBE and RDRAND support to the instruction set which brings the extension feature set close to Intel's Haswell. Since the targeted platforms for these APUs are notebooks, all-in-ones and convertibles, they will be shipped in BGA )FP4) packet and volition transport in variants ranging in TDPs of 12/15/35W.

The most interesting affair about Carrizo, aside from its technical specifications is likewise the design of the chip itself. AMD for the first time is aiming for a truthful SOC design eliminating the need of a separate FCH as was the instance with Kaveri mobile which requires Bolton FCH for additional connectivity options. The FCH will be integrated on the dice itself which will deliver Security, Display, Sound, PCI-e, SATA, SD, USB, Multimedia, UART/12C. CLCKGen and Misc I/O connectivity. AMD is aiming for UVD6, VCE3 and a audio co-processors with H.264 encode while characteristic a display control engine "DCE11″. With HDMI 2.0 that provides upwardly to iii display interfaces and PCI-e Gen three.0 x8 for discrete GPU expansion and PCI-due east iii.0 x4 for GPP, the APU begins to look like a decent improvement over Kaveri from a design perspective. The FCH can deliver iv USB 3.0 / 2.0 ports, 4 USB ii.0 ports and two SATA three ports while the memory controller allow for Dual Channel DDR3 retentiveness rated at 2133 MHz in SoDIMM form cistron (One per channel).

AMD FX-8800P Could Be Flagship Carrizo Mobile APU - 3DMark Criterion Revealed

The listing of an AMD FX-8800P came all suddenly when AMD is nevertheless a few months away from launching their Carrizo mobile APU. The terminal flagship APU that was part of AMD's Kaveri family was codenamed FX-7600P and the FX-8800P seems to be its successor from the Carrizo APU family. The 3DMark criterion is vague on specs and details but it does list the FX-8800P as a 12 Compute Cores enabled office which confirms that the Carrizo APU on mobility will characteristic a maximum of iv x86 Excavator cores and 8 GCN Compute units forming into the 12 Compute Cores which AMD has been branding since the launch of Kaveri (considering the can be used as GPGPU). The testing was performed on the AMD Gardenia platform which is an internal codename for the test lath that is used to run Carrizo samples. Remainder of the specifications include the Radeon R7 graphics branding for the 512 SPs iGPU and a preliminary clock speed of one.seven GHz base and 2.1 GHz boost. The flake scores around 2645 points in 3DMark 11 functioning manner which can be compared to the 2150 (average performance) score of the Kaveri based FX-7600P APU.

AMD Carrizo is expected to hit the mobility marketplace in mid of 2022 and the AMD presentation at ISSCC 2022 commences on 23rd February (iv:45 PM Pacific US Time) and so more details are expected but nothing that we know already.

AMD Carrizo APU ISSCC 2022 Slides (Courtesy of Videocardz)

AMD x86 Excavator Core Block Diagram:

AMD Carrizo APU Official Presentation Slides:

AMD Carrizo APU Comparison Nautical chart:

	AMD Trinity APU	AMD Richland APU	AMD Kaveri APU	AMD Carrizo-L	AMD Carrizo APU
Cadre	x86 Piledriver	x86 Piledriver	x86 Steamroller	x86 PUMA+	x86 Excavator
Cores	two-4	two-iv	2-iv	two-four	2-4
GPU	Hd 7000 VLIW4	Hard disk 8000 VLIW4	2nd GCN Bounding main Islands	2nd GCN Body of water Islands	third GCN Volcanic Islands
GCN Cores	384 SPs	384 SPs	512 SPs	128 SPs?	512 SPs
Chipset	A85X/A75/FCH	A88X/A78/FCH	A88X/A78/Bolton	SOC	SOC
Socket	FM2/FM2+/BGA	FM2/FM2+/BGA	FM2+/BGA	BGA	BGA
Memory	DDR3	DDR3	DDR3	DDR3	DDR3
TDP	17/25/35W	17/25/35W	17/19/35W	x/25W	15-35W
HSA Support	No	No	Yes	Aye	Full HSA i.0